Methodological Framework for NoC Resources Dimensioning on FPGAs | Zendy

Virginie Fresse | Zendy; Catherine Combes | Zendy; M. Payet | Zendy; Frédéric Rousseau | Zendy

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Methodological Framework for NoC Resources Dimensioning on FPGAs

Author(s) -

Virginie Fresse,

Catherine Combes,

M. Payet,

Frédéric Rousseau

Publication year - 2015

Publication title -

procedia computer science

Language(s) - English

Resource type - Journals

SCImago Journal Rank - 0.334

H-Index - 76

ISSN - 1877-0509

DOI - 10.1016/j.procs.2015.07.225

Subject(s) - computer science , dimensioning , field programmable gate array , task (project management) , graph , architecture , computer architecture , network on a chip , field (mathematics) , embedded system , distributed computing , theoretical computer science , art , management , engineering , economics , visual arts , aerospace engineering , mathematics , pure mathematics

The two main challenges involved in prototyping a SoC (System-On-Chip) on a FPGA (field programmable gate array) are optimal tuning of the communication architecture according to the task graph of an application, and dimensioning the FPGA resources. In this paper, we present a methodological framework to estimate the number of resources required for a given communication architecture and task graph. Data analysis was based on a set of synthesized results for a given on-chip network. The most appropriate models were identified using a data mining approach. The evaluation of the models shows that the relative error is less than 5% in most cases. It is therefore possible to estimate the required resources in a short exploration time and without the synthesis steps

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