TRAMS Project: Variability and Reliability of SRAM Memories in sub-22nm Bulk-CMOS Technologies | Zendy

R. Canal | Zendy; Antonio J. Rubio | Zendy; Asen Asenov | Zendy; Alexander L. Brown | Zendy; M. Miranda | Zendy; Paul Zuber | Zendy; Antonio González | Zendy; Xavier Vera | Zendy

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TRAMS Project: Variability and Reliability of SRAM Memories in sub-22nm Bulk-CMOS Technologies

Author(s) -

R. Canal,

Antonio J. Rubio,

Asen Asenov,

Alexander L. Brown,

M. Miranda,

Paul Zuber,

Antonio González,

Xavier Vera

Publication year - 2011

Publication title -

procedia computer science

Language(s) - English

Resource type - Journals

SCImago Journal Rank - 0.334

H-Index - 76

ISSN - 1877-0509

DOI - 10.1016/j.procs.2011.09.010

Subject(s) - cmos , computer science , static random access memory , reliability (semiconductor) , scaling , electronic circuit , embedded system , computer architecture , electronic engineering , electrical engineering , computer hardware , power (physics) , physics , geometry , mathematics , quantum mechanics , engineering

The TRAMS (Terascale Reliable Adaptive MEMORY Systems) project addresses in an evolutionary way the ultimate CMOS scaling technologies and paves the way for revolutionary, most promising beyond-CMOS technologies. In this abstract we show the significant variability levels of future 18 and 13nm device bulk-CMOS technologies as well as its dramatic effect on the yield of memory cells and circuits

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