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Design of the ATLAS IBL Readout System
Author(s) -
A. Polini,
G. Bruni,
M. Bruschi,
I. DʼAntone,
J. Dopke,
D. Falchieri,
T. Flick,
A. Gabrielli,
J. Große-Knetter,
John Joseph,
Nina Krieger,
A. Kugel,
P. Morettini,
Matteo Rizzi,
Nicolai Schroer,
R. Travaglini,
Samuele Zannoli,
A. Zoccoli
Publication year - 2012
Publication title -
physics procedia
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.26
H-Index - 61
ISSN - 1875-3892
DOI - 10.1016/j.phpro.2012.02.524
Subject(s) - upgrade , detector , gigabit , atlas (anatomy) , pixel , computer hardware , computer science , calibration , data acquisition , backplane , electronics , electrical engineering , physics , embedded system , telecommunications , operating system , artificial intelligence , engineering , paleontology , quantum mechanics , biology
An Insertable B-Layer is planned for the upgrade of the ATLAS detector and will add a fourth and innermost silicon layer to the existing Pixel Detector. 12 million pixels attached to new FE-I4 readout ASICs will require new off-detector electronics which is currently realized with two VME-based boards: a Back Of Crate module implementing optical I/O functionality and a Readout Driver module for data processing. This paper illustrates the new read-out chain, focusing on the design of the new Readout Driver Card, which, with a fourfold integration with respect to the previous design, builds up the detector data, controls the calibration procedures and interacts via Gigabit links with a novel calibration farm. Future prospects and back compatibility to the existing system are also addressed

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