New design approaches of reversible BCD encoder using Peres and Feynman gates | Zendy

Sheba Diamond Thabah | Zendy; Prabir Saha | Zendy

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New design approaches of reversible BCD encoder using Peres and Feynman gates

Author(s) -

Sheba Diamond Thabah,

Prabir Saha

Publication year - 2019

Publication title -

ict express

Language(s) - English

Resource type - Journals

SCImago Journal Rank - 0.733

H-Index - 22

ISSN - 2405-9595

DOI - 10.1016/j.icte.2019.07.001

Subject(s) - decimal , feynman diagram , arithmetic , reduction (mathematics) , encoder , toffoli gate , gate count , state (computer science) , logic gate , binary number , computer science , quantum gate , mathematics , algorithm , discrete mathematics , computer hardware , quantum computer , quantum , quantum mechanics , physics , operating system , geometry , mathematical physics

This paper proposes two new design approaches for decimal to binary-coded-decimal (BCD) encoder using reversible logic through Peres gate (PG) and Feynman gate (FG) which consume 10 and 11 gates respectively to realize such circuitry. Gates have been arranged properly to minimize the gate count (GC) followed by the reduction of the quantum cost (QC) and garbage outputs (GO). The proposed designs have an improvement at least up to ∼ 45%, ∼ 40%, and ∼ 50% of GC, GO and QC respectively from the best state of the art designs.

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