Asynchronous Logic Circuits and Sheaf Obstructions | Zendy

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Asynchronous Logic Circuits and Sheaf Obstructions

Author(s) -

Michael Robinson

Publication year - 2012

Publication title -

electronic notes in theoretical computer science

Language(s) - English

Resource type - Journals

SCImago Journal Rank - 0.242

H-Index - 60

ISSN - 1571-0661

DOI - 10.1016/j.entcs.2012.05.010

Subject(s) - sheaf , asynchronous circuit , computer science , sequential logic , existential quantification , theoretical computer science , logic optimization , formalism (music) , electronic circuit , logic gate , truth table , mathematics , algorithm , logic synthesis , programming language , discrete mathematics , electrical engineering , pure mathematics , engineering , clock signal , synchronous circuit , art , musical , visual arts

This article exhibits a particular encoding of logic circuits into a sheaf formalism. The central result of this article is that there exists strictly more information available to a circuit designer in this setting than exists in static truth tables, but less than exists in event-level simulation. This information is related to the timing behavior of the logic circuits, and thereby provides a “bridge” between static logic analysis and detailed simulation

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