Geometry of Synthesis II: From Games to Delay-Insensitive Circuits | Zendy

Dan R. Ghica | Zendy; Alex Smith | Zendy

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Geometry of Synthesis II: From Games to Delay-Insensitive Circuits

Author(s) -

Dan R. Ghica,

Alex Smith

Publication year - 2010

Publication title -

electronic notes in theoretical computer science

Language(s) - English

Resource type - Journals

SCImago Journal Rank - 0.242

H-Index - 60

ISSN - 1571-0661

DOI - 10.1016/j.entcs.2010.08.018

Subject(s) - computer science , concurrency , correctness , compiler , asynchronous communication , programming language , context (archaeology) , mathematical proof , very large scale integration , asynchronous circuit , digital electronics , electronic circuit , theoretical computer science , mathematics , embedded system , geometry , computer network , paleontology , telecommunications , jitter , clock signal , synchronous circuit , biology , electrical engineering , engineering

This paper extends previous work on the compilation of higher-order imperative languages into digital circuits [Ghica, D.R., Geometry of Synthesis: a structured approach to VLSI design, in: POPL, 2007, pp. 363–375.]. We introduce concurrency, an essential feature in the context of hardware compilation and we re-use an existing game model to simplify correctness proofs. The target designs we compile to are asynchronous event-logic circuits, which naturally match the asynchronous game model of the language

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