Model Based Testing of a Network-on-Chip Component | Zendy

Leonidas Tsiopoulos | Zendy; Manoranjan Satpathy | Zendy

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Model Based Testing of a Network-on-Chip Component

Author(s) -

Leonidas Tsiopoulos,

Manoranjan Satpathy

Publication year - 2009

Publication title -

electronic notes in theoretical computer science

Language(s) - English

Resource type - Journals

SCImago Journal Rank - 0.242

H-Index - 60

ISSN - 1571-0661

DOI - 10.1016/j.entcs.2009.09.054

Subject(s) - computer science , asynchronous communication , component (thermodynamics) , model based testing , formalism (music) , test case , automatic test pattern generation , theoretical computer science , machine learning , engineering , art , computer network , musical , physics , regression analysis , electrical engineering , visual arts , thermodynamics , electronic circuit

We discuss the problem of model based test case generation and that of automatic testing of a component of an asynchronous Network-on-Chip (NoC). We start with a model of the component in B Action System, which is a state based formalism based on Action Systems and the B Method. We construct a finite state space graph by executing the model, and next, generate a test driver from the abstract test cases. This test driver can be used to test a matching implementation automatically. The important contribution of our work is that we consider hierarchical models for test case generation and automatic testing, whereas the previous approaches considered flat models. In addition, we also highlight the issue due to non-determinism in hierarchical models

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