Opportunities and Challenges in Process-algebraic Verification of Asynchronous Circuit Designs | Zendy

Xu Wang | Zendy; Marta Kwiatkowska | Zendy; Georgios Theodoropoulos | Zendy; Qingfu Zhang | Zendy

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Opportunities and Challenges in Process-algebraic Verification of Asynchronous Circuit Designs

Author(s) -

Xu Wang,

Marta Kwiatkowska,

Georgios Theodoropoulos,

Qingfu Zhang

Publication year - 2006

Publication title -

electronic notes in theoretical computer science

Language(s) - English

Resource type - Journals

SCImago Journal Rank - 0.242

H-Index - 60

ISSN - 1571-0661

DOI - 10.1016/j.entcs.2005.05.042

Subject(s) - computer science , asynchronous communication , programming language , abstraction , implementation , process (computing) , computer architecture , syntax , asynchronous circuit , theoretical computer science , artificial intelligence , synchronous circuit , computer network , telecommunications , philosophy , epistemology , clock signal , jitter

This paper reports our experiences of applying process algebras and associated tools (esp. CSP/FDR2) to verify asynchronous circuit designs developed in the Balsa environment. Balsa is an asynchronous logic synthesis system which uses syntax-directed compilation to generate gate-level implementations from high-level descriptions in a parallel programming language (also called Balsa). Previously, we have proposed a unifying approach to compositionally verifying Balsa designs across several abstraction levels. This paper continues our effort by applying and testing our approach on several large-scale real-life case studies. We describe the outcome of verification for the case studies, and also analyse the strengths and limitations of our method

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