A Low-Cost Jitter Measurement Technique for BIST Applications | Zendy

Jiun-Lang Huang | Zendy; Jui-Jer Huang | Zendy; Yuan-Shuang Liu | Zendy

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A Low-Cost Jitter Measurement Technique for BIST Applications

Author(s) -

Jiun-Lang Huang,

Jui-Jer Huang,

Yuan-Shuang Liu

Publication year - 2006

Publication title -

journal of electronic testing

Language(s) - English

Resource type - Journals

SCImago Journal Rank - 0.247

H-Index - 34

eISSN - 1573-0727

pISSN - 0923-8174

DOI - 10.1007/s10836-006-8600-0

Subject(s) - jitter , gaussian , field programmable gate array , signal (programming language) , computer science , electronic engineering , built in self test , algorithm , engineering , computer hardware , physics , quantum mechanics , programming language

In this paper, we present a BIST technique that measures the RMS value of a Gaussian distribution period jitter. In the proposed approach, the signal under test is delayed by two different delay values and the probabilities it leads the two delayed signals are measured. The RMS jitter can then be derived from the probabilities and the delay values. Behavior and circuit simulations are performed to validate the proposed technique and analyze the design tradeoffs, and preliminary measurement results on FPGA are also presented.

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