A systematic incrementalization technique and its application to hardware design
Author(s) -
Steven D. Johnson,
Yanhong A. Liu,
Yuchen Zhang
Publication year - 2003
Publication title -
international journal on software tools for technology transfer
Language(s) - English
Resource type - Book series
SCImago Journal Rank - 0.397
H-Index - 55
eISSN - 1433-2787
pISSN - 1433-2779
ISBN - 3-540-66559-5
DOI - 10.1007/s100090100067
Subject(s) - computer science , theory of computation , rewriting , automated theorem proving , task (project management) , transformation (genetics) , program transformation , reduction (mathematics) , gas meter prover , square root , programming language , computer engineering , theoretical computer science , parallel computing , algorithm , mathematics , mathematical proof , biochemistry , chemistry , geometry , management , economics , gene
. A systematic transformation method based on incrementalization and value caching generalizes a broad family of program optimizations. It yields significant performance improvements in many program classes, including iterative schemes that characterize hardware specifications. CACHET is an interactive incrementalization tool. Although incrementalization is highly structured and automatable, better results are obtained through interaction, where the main task is to guide term rewriting based on data-specific identities. Incrementalization specialized to iteration corresponds to strength reduction, a familiar program improvement technique. This correspondence is illustrated by the derivation of a hardware-efficient nonrestoring square-root algorithm, which has also served as an example of theorem prover-based implementation verification.
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