A design environment for counterflow pipeline synthesis | Zendy

Bruce R. Childers | Zendy; Jack W. Davidson | Zendy

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A design environment for counterflow pipeline synthesis

Author(s) -

Bruce R. Childers,

Jack W. Davidson

Publication year - 1998

Publication title -

lecture notes in computer science

Language(s) - English

Resource type - Book series

SCImago Journal Rank - 0.249

H-Index - 400

eISSN - 1611-3349

pISSN - 0302-9743

ISBN - 3-540-65075-X

DOI - 10.1007/bfb0057793

Subject(s) - heuristics , pipeline (software) , speedup , computer science , simple (philosophy) , parallel computing , computer engineering , distributed computing , computer architecture , programming language , operating system , philosophy , epistemology

The Counterflow Pipeline (CFP) organization may be a good target for synthesis of application-specific microprocessors for embedded systems because it has a regular and simple structure. This paper describes a design environment for tailoring CFP''s to an embedded application to improve performance. Our system allows exploring the design space of all possible CFP''s for a given application to understand the impact of different design decisions on performance. We have used the environment to derive heuristics that help to find the best CFP for an application. Preliminary results using our heuristics indicate that speedup for several small graphs range from 1.3 to 2.0 over a general-purpose CFP and that the heuristics find designs that are within 10% of optimal.

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