Open AccessVerification of Switch-level designs with many-valued logic
Author(s) -
Reiner Hähnle,
Werner Kernig
Publication year - 1993
Publication title -
lecture notes in computer science
Language(s) - English
Resource type - Book series
SCImago Journal Rank - 0.249
H-Index - 400
eISSN - 1611-3349
pISSN - 0302-9743
ISBN - 3-540-56944-8
DOI - 10.1007/3-540-56944-8_50
Subject(s) - soundness , computer science , automated theorem proving , electronic circuit , theoretical computer science , gas meter prover , logic gate , algorithm , programming language , computer engineering , arithmetic , mathematics , mathematical proof , electrical engineering , geometry , engineering
This paper is an approach to automated verification of circuits represented as switch level designs. Switch level models (SLM) are a well established framework for modelling low level properties of circuits. We use many valued propositional logic to represent a suitable variant of SLM. Logical properties of circuits (gate level) can be expressed in a standard way in the same logic. As a result we can express soundness of switch level designs wrt to gate level specifications as many valued...
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