Dynamic Tag-Check Omission: A Low Power Instruction Cache Architecture Exploiting Execution Footprints | Zendy

Koji Inoue | Zendy; Vasily G. Moshnyaga | Zendy; Kazuaki Murakami | Zendy

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Dynamic Tag-Check Omission: A Low Power Instruction Cache Architecture Exploiting Execution Footprints

Author(s) -

Koji Inoue,

Vasily G. Moshnyaga,

Kazuaki Murakami

Publication year - 2003

Publication title -

lecture notes in computer science

Language(s) - English

Resource type - Book series

SCImago Journal Rank - 0.249

H-Index - 400

eISSN - 1611-3349

pISSN - 0302-9743

ISBN - 3-540-01028-9

DOI - 10.1007/3-540-36612-1_2

Subject(s) - cache , computer science , cache algorithms , cache pollution , cache coloring , smart cache , parallel computing , cache invalidation , page cache , reduction (mathematics) , operating system , cpu cache , embedded system , geometry , mathematics

We present the high-level microarchitecture of LPX: a low-power issue-execute processor prototype that is being designed by a joint industry-academia research team. LPX implements a very small subset of a RISC architecture, with a primary focus on a vector (SIMD) multi-media extension. The objective of this project is to validate some key new ideas in power-aware microarchitecture techniques, supported by recent advances in circuit design and clocking.

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