Improving the Performance of GCC by Exploiting IA-64 Architectural Features | Zendy

Canqun Yang | Zendy; Xuejun Yang | Zendy; Jingling Xue | Zendy

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Improving the Performance of GCC by Exploiting IA-64 Architectural Features

Author(s) -

Canqun Yang,

Xuejun Yang,

Jingling Xue

Publication year - 2005

Publication title -

lecture notes in computer science

Language(s) - English

Resource type - Book series

SCImago Journal Rank - 0.249

H-Index - 400

eISSN - 1611-3349

pISSN - 0302-9743

ISBN - 3-540-29643-3

DOI - 10.1007/11572961_20

Subject(s) - computer science , compiler , parallel computing , loop unrolling , alias , loop optimization , optimizing compiler , set (abstract data type) , point (geometry) , performance improvement , parallelism (grammar) , instruction level parallelism , computer architecture , programming language , operations management , geometry , mathematics , database , economics

The IA-64 architecture provides a rich set of features to aid the compiler in exploiting instruction-level parallelism to achieve high performance. Currently, GCC is a widely used open-source compiler for IA-64, but its performance, especially its floating-point performance, is poor compared to that of commercial compilers because it has not fully utilized IA-64 architectural features. Since late 2003 we have been working on improving the performance of GCC on IA-64. This paper reports four improvements on enhancing its floating-point performance, namely alias analysis for FORTRAN (its part for COMMON variables already committed in GCC 4.0.0), general induction variable optimization, loop unrolling and prefetching arrays in loops. These improvements have significantly improved the floating-point performance of GCC on IA-64 as extensively validated using SPECfp2000 and NAS benchmarks.

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