Combination of Isabelle/HOL with Automatic Tools

We describe results and status of a sub project of the Verisoft (1) project. While the Verisoft project aims at verification of a complete computer system starting with hardware and up to user applications, the goal of our sub project is an efficient hardware verification. We use the Isabelle theorem prover (2) as the major tool for hardware design and verification. Since many hardware verification problems can be efficiently solved by automatic tools, we combine Isabelle with model checkers and SAT solvers. This combination of tools speeds up verification of hardware and sim- plifies sharing of the results with verification of the whole computer system. To increase the range of problems which can be solved by external tools we imple- mented in Isabelle several algorithms for handling uninterpreted functions and data abstraction. The resulting combination was applied to verify many different hardware cir- cuits, automata, and processors. In our project we use open source tools that are free for academical and com- mercial purposes.