PID and low‐order controller design for guaranteed delay margin and pole placement

This article provides a simple low‐order controller design method (including PID controllers as special cases) for a class of unstable systems. First, PID controller design is considered for systems with two unstable poles and pole placement and delay margin issues are discussed. Then, a chain of integrators is considered with arbitrary stable dynamics in cascade. For a given desired minimum delay margin for this class of plants, a PID and low‐order controller design method is obtained in terms of an inequality constraint on the sum of k of the desired closed‐loop poles, where k is number of the integrators in the open‐loop transfer function.