Fabrication of nanocrystal memories by ultra low energy ion implantation

In silicon nanocrystal based metal‐oxide‐semiconductor memory structures, tuning of the electron tunneling distance between the Si substrate and Si nanocrystals located in the gate oxide is a crucial requirement for the pinpointing of optimal device architectures. In this work, we show how to manipulate and control the depth‐position and the density of 2D arrays of Si ncs embedded in thin (<10 nm) SiO 2 layers, fabricated by ultra‐low energy (typically 1 keV) ion implantation. It is demonstrated that the injection distance between the ncs band and the channel can be tuned from 10 to 2 nm by a judicious combination of ion beam energy and initial SiO 2 thickness. Annealing under slightly oxidizing ambient has been found essential for the optimization of the memory properties of the devices. During such oxidations, the oxide integrity is restored, the ncs are passivated and a separation of connected ncs takes place, making possible a further increase of the ncs density and a decrease of their mean size. (© 2005 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)