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Circuit discovery has gradually become one of the prominent methods formechanistic interpretability, and research on circuit completeness has alsogarnered increasing attention. Methods of circuit discovery that do notguarantee completeness not only result in circuits that are not fixed acrossdifferent runs but also cause key mechanisms to be omitted. The nature ofincompleteness arises from the presence of OR gates within the circuit, whichare often only partially detected in standard circuit discovery methods. Tothis end, we systematically introduce three types of logic gates: AND, OR, andADDER gates, and decompose the circuit into combinations of these logicalgates. Through the concept of these gates, we derive the minimum requirementsnecessary to achieve faithfulness and completeness. Furthermore, we propose aframework that combines noising-based and denoising-based interventions, whichcan be easily integrated into existing circuit discovery methods withoutsignificantly increasing computational complexity. This framework is capable offully identifying the logic gates and distinguishing them within the circuit.In addition to the extensive experimental validation of the framework's abilityto restore the faithfulness, completeness, and sparsity of circuits, using thisframework, we uncover fundamental properties of the three logic gates, such astheir proportions and contributions to the output, and explore how they behaveamong the functionalities of language models.

Rethinking Circuit Completeness in Language Models: AND, OR, and ADDER Gates