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Capacitive sensors that utilize the Coplanar Interdigitated (CID) electrode structure are widely employed in various technical and analytical domains, such as healthcare, infectious disease management, pharmaceuticals, metrology, and environmental monitoring. The present exigency for lab-on-a-chip contrivances and the requisite for the miniaturization of sensors have led to the widespread adoption of CID sensors featuring multiple dielectric layers (DLs), either in the form of substrates or superstrates. Previously, we derived an analytical model for the capacitance of CID capacitive sensors with four distinct 1-N-1 patterns (namely, 1-1-1, 1-3-1, 1-5-1, and 1-11-1) using partial capacitance (PC) and conformal mapping (CM) techniques. The aforementioned model has been employed in various applications wherein the permittivity of successive layers exhibits a monotonic decrease as one moves away from the electrode plane, resulting in highly satisfactory outcomes. Nevertheless, the PC technique is inadequate for structures with multiple layers where the permittivity exhibits a monotonic increase as the distance from the electrodes increases. Given these circumstances, it is necessary to adapt the initial PC method to incorporate these novel configurations. In this work, we have discussed a new approach, splitting the concept of PC into partial parallel capacitance (PPC) and partial serial capacitance (PSC), where new CM transformations are proposed for the latter case. Thus, the present study proposes a novel methodology to expand upon our prior analytical framework, which aims to incorporate scenarios where the permittivity experiences a reduction across successive layers. The outcomes are juxtaposed with the finite element simulation and analytical findings.

Expansion of the Analytical Modeling of Capacitance for 1-N-1 Multilayered CID Structures with Monotonically Increasing/Decreasing Permittivity