Open AccessLow Power Digital Design using Asynchronous Logic
Author(s) -
Antony Jayasekar,
Sathish Vimalraj
Publication year - 2019
Language(s) - Uncategorized
Resource type - Dissertations/theses
DOI - 10.31979/etd.vzps-r5xf
Subject(s) - asynchronous circuit , asynchronous communication , asynchronous system , computer science , verilog , synchronous circuit , embedded system , logic synthesis , clock signal , sequential logic , state (computer science) , power (physics) , register transfer level , electronic engineering , logic gate , computer hardware , engineering , field programmable gate array , telecommunications , jitter , physics , algorithm , quantum mechanics