Open AccessLow Power Digital Design using Asynchronous Logic
Author(s) -
Sathish Vimalraj Antony Jayasekar
Publication year - 2011
Language(s) - Uncategorized
Resource type - Dissertations/theses
DOI - 10.31979/etd.vzps-r5xf
Subject(s) - asynchronous circuit , asynchronous communication , computer science , asynchronous system , verilog , embedded system , synchronous circuit , logic synthesis , clock signal , sequential logic , state (computer science) , register transfer level , power (physics) , compiler , electronic engineering , logic gate , computer hardware , engineering , field programmable gate array , telecommunications , jitter , algorithm , programming language , quantum mechanics , physics
Accelerating Research
Robert Robinson Avenue,
Oxford Science Park, Oxford
OX4 4GP, United Kingdom
Address
John Eccles HouseRobert Robinson Avenue,
Oxford Science Park, Oxford
OX4 4GP, United Kingdom