Open AccessFPGA Implementation of Low Power High Speed BTED Algorithm for 8 Bit Error Correction in Cryptography System
Author(s) -
M Ramesha
Publication year - 2020
Publication title -
international journal of emerging trends in engineering research
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.218
H-Index - 14
ISSN - 2347-3983
DOI - 10.30534/ijeter/2020/158872020
Subject(s) - field programmable gate array , computer science , cryptography , bit (key) , algorithm , power analysis , computer hardware , computer security
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