Open AccessFPGA Implementation of 16-bit Multipliers based upon Vedic Mathematic Approach
Author(s) -
Zulhelmi
Publication year - 2014
Publication title -
jurnal rekayasa elektrika
Language(s) - English
Resource type - Journals
eISSN - 2252-620X
pISSN - 1412-4785
DOI - 10.17529/jre.v10i4.1105
Subject(s) - field programmable gate array , multiplier (economics) , computer science , digital signal processing , computer hardware , adder , embedded system , arithmetic , mathematics , telecommunications , economics , macroeconomics , latency (audio)