CMOS based Power Efficient Digital Comparator with Parallel Prefix Tree Structure
Author(s) -
J Lakshmi Prasanna,
V Sahiti,
E Raghuveera,
Mohit Kumar
Publication year - 2018
Publication title -
international journal of engineering and technology
Language(s) - English
Resource type - Journals
ISSN - 2227-524X
DOI - 10.14419/ijet.v7i2.7.10915
Subject(s) - comparator , transmission gate , cmos , computer science , least significant bit , electronic engineering , logic gate , digital electronics , pass transistor logic , computer hardware , electrical engineering , electronic circuit , engineering , transistor , algorithm , voltage , operating system
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