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We present a novel approach to the modeling of carrier energy relaxation during high-field phases in semiconductor-oxide-nitride-oxide-semiconductor (SONOS) flash memory gate stacks. We show that this method integrates well with TCAD simulators and that taking the energy relaxation of carriers into consideration solves two of the most prominent problems of trapping layer dynamics modeling: The missing slope degradation in incremental step-pulse programming (ISPP) simulations and the incompatibility of the resulting charge distributions with long-term room temperature charge retention measurements. This article consists of two parts where this part discusses the physical/TCAD level. The second part derives a semianalytical model specifically for programming that reduces the numerical complexity while still retaining the main physical assumptions and the applicability to experimental data.

Modeling the Operation of Charge Trap Flash Memory–Part I: The Importance of Carrier Energy Relaxation