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Characterizing mixed hot-carrier/bias temperature instability (BTI) degradation in full {VG, VD} bias space is a challenging task. Therefore, studies usually focus on individual degradation mechanisms, such as BTI and hot-carrier degradation (HCD). However, a simple superposition of these mechanisms at an arbitrary {VG, VD} combination often fails to predict the cumulative damage. We experimentally acquired a large data set covering the full bias space of a pMOSFET which allows us to obtain detailed degradation and recovery maps. Our models for describing oxide and interface defects provide physical insights into the underlying mechanisms and a possible interplay between the degradation modes. Additionally, we perform a dedicated experiment to reveal the implications of different stress regimes onto the various types of defects by switching BTI and HCD stress conditions.The results clearly reveal the conceptual limits of the assumption of independent degradation regimes.

ieee transactions on electron devices

Mixed Hot-Carrier/Bias Temperature Instability Degradation Regimes in Full &#x007B;<italic>V</italic>G, <italic>V</italic>D&#x007D; Bias Space: Implications and Peculiarities

Mixed Hot-Carrier/Bias Temperature Instability Degradation Regimes in Full {VG, VD} Bias Space: Implications and Peculiarities

Mixed Hot-Carrier/Bias Temperature Instability Degradation Regimes in Full {V_G, V_D} Bias Space: Implications and Peculiarities