English (United Kingdom)

https://curated-unify.zendy.io/wp-json/zendy-region/v1/featured_content/oa?rat=en

https://curated-unify.zendy.io/wp-json/zendy-region/v1/highlighted_journal/

Global: Zendy Plus annual

Presents the access of premium content as premium feature

Premium Content

Presents the keyphrase highlighting as premium feature

Keyphrase Highlighting

Presents the summarisation as premium feature

Summarisation

Insights

Presents the pdf analysis as premium feature

PDF Analysis

Presents the zaia usage as premium feature

ZAIA

Global: Zendy Plus monthly

Global: Zendy Tools annual

Global: Zendy Tools monthly

Global: Zendy Free Plan

Ge is a candidate for replacing Si, especially for pMOSFETs, because of its high hole mobility. For Si-pMOSFETs, negative-bias temperature instabilities (NBTI) limit their lifetime. There is little information available for the NBTI of Ge-pMOSFETs with <inline-formula> <tex-math notation="TeX">${\rm Ge}/{\rm GeO}_{2}/{\rm Al}_{2}{\rm O}_{3}$ </tex-math></inline-formula> stack. The objective of this paper is to provide this information and compare the NBTI of Ge- and Si-pMOSFETs. New findings include: 1) the time exponent varies with stress biases/field when measured by either the conventional slow dc or pulse <inline-formula> <tex-math notation="TeX">$I{-}V$ </tex-math></inline-formula> technique, making the conventional <inline-formula> <tex-math notation="TeX">$V_{\rm g}$ </tex-math></inline-formula>-accelerated method for predicting the lifetime of Si-pMOSFETs inapplicable to Ge-pMOSFETs used in this paper; 2) the NBTI is dominated by positive charges (PCs) in dielectric, rather than generated interface states; 3) the PC in <inline-formula> <tex-math notation="TeX">${\rm Ge}/{\rm GeO}_{2}/{\rm Al}_{2}{\rm O}_{3}$ </tex-math></inline-formula> can be fully annealed at 150<inline-formula> <tex-math notation="TeX">$^{\circ}{\rm C}$ </tex-math></inline-formula>; and 4) the defect losses reported for Si sample were not observed. For the first time, we report that the PCs in oxides on Ge and Si behave differently, and to explain the difference, an energy-switching model is proposed for hole traps in Ge-MOSEFTs: their energy levels have a spread below the edge of valence band, i.e., <inline-formula> <tex-math notation="TeX">$E_{\rm v}$ </tex-math></inline-formula>, when neutral, lift well above <inline-formula> <tex-math notation="TeX">$E_{\rm v}$ </tex-math></inline-formula> after charging, and return below <inline-formula> <tex-math notation="TeX">$E_{\rm v}$ </tex-math></inline-formula> following neutralization.

ieee transactions on electron devices

Characterization of Negative-Bias Temperature Instability of Ge MOSFETs With <inline-formula> <tex-math notation="TeX">${\rm GeO}_{2}/{\rm Al}_{2}{\rm O}_{3}$ </tex-math></inline-formula> Stack

Characterization of Negative-Bias Temperature Instability of Ge MOSFETs With ${\rm GeO}_{2}/{\rm Al}_{2}{\rm O}_{3}$ Stack