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This letter describes a fully synthesizable fractional-N multiplexing delay-locked loop (MDLL) with a ring-oscillator-based digital-to-time converter (RO-DTC). The proposed RO-DTC can generate a wide range of time delays with only a relatively smaller number of delay cells. Since its structure is periodical, the corresponding pre-distortion look-up table (LUT)&#x2019;s size could also be reduced. The proposed MDLL is implemented in a 65-nm CMOS process. The measured results show that the RO-DTC&#x2019;s power normalized by operating frequency and tuning range is the lowest among other state-of-the-art works. The proposed MDLL achieves FoMs of &#x2013;242.3dB and &#x2013;218.6dB in integer-N and fractional-N operation modes at RF frequencies 1.04GHz and 1.0465GHz. The core area is 0.0892mm.

A Fully Synthesizable Fractional-N MDLL With Energy-Efficient Ring-Oscillator-Based DTC of Large Tuning Range