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We demonstrate two 8 <inline-formula> <tex-math notation="TeX">$\times$</tex-math></inline-formula> 1 silicon ring resonator (RR)-based multiplexers (MUXs) integrated on the same chip for dual-stream 16-channel multiplexing/demultiplexing applications. Cascaded second-order RRs equipped with microheaters were integrated on a silicon-on-insulator platform with the radii of MUX1 and MUX2 being <inline-formula> <tex-math notation="TeX">$\sim\!\! 12$</tex-math></inline-formula> and <inline-formula> <tex-math notation="TeX">$\sim\!\! 9\ \mu\hbox{m}$</tex-math></inline-formula>, respectively. The resonances of the two MUXs were thermooptically tuned in order to achieve 100-GHz channel spacing, revealing a tuning efficiency of 43 and 36 <inline-formula> <tex-math notation="TeX">$\mu \hbox{W}$</tex-math></inline-formula>/GHz/RR for MUX1 and MUX2, respectively, and 352 mW total power consumption. Lower than <inline-formula> <tex-math notation="TeX">$\sim$</tex-math></inline-formula>18 dB crosstalk and higher than <inline-formula> <tex-math notation="TeX">$\sim$</tex-math></inline-formula>40-GHz 3-dB bandwidth was obtained for the tuned channels of the MUXs. The signal integrity when using these devices in multiplexing and demultiplexing operations was evaluated for a 4 <inline-formula> <tex-math notation="TeX">$\times$</tex-math></inline-formula> 10 Gb/s non-return-to-zero data stream (i.e., 10 Gb/s line rate) via bit-error-rate measurements, yielding error-free performance with up to 0.2 dB power penalty for all channels. Proof-of-concept demonstration for supporting higher data rates was also realized by using three 100-GHz-spaced 25-Gb/s return-to-zero data signals (i.e., 25 Gb/s line rate) for multiplexing and demultiplexing via MUX2, resulting in error-free operation for all channels with lower than 0.3 dB power penalties

On-Chip Dual-Stream DWDM Eight-Channel-Capable SOI-Based MUX s/DEMUX s With 40-GH z Channel Bandwidth