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In-memory computing (IMC) has emerged as one of the most promising candidates for distributed computing frameworks such as edge computing, owing to its unrivalled energy efficiency and high throughput. By leveraging arrays of emerging devices, such as resistive random access memories (RRAM), to implement massive parallel computation, IMC overcomes the main limitations of classic von Neumann architectures. Meanwhile, next generation telecommunication networks are bound to rely ever more intensively on matrix computations to allow simultaneous transmission and reception over multiple spatial channels, an approach known as Massive Multiple-Input Multiple-Output (MIMO). Here, we propose a closed-loop in-memory computing circuit for the acceleration of Ridge Regression, an algebraic prior that finds application in all phases of a typical massive MIMO transaction, namely channel estimation, uplink and downlink. Particularly, we show the circuit&#x2019;s capability to perform Zero-Forcing (ZF) and Regularized Zero-Forcing (RZF) detection and beamforming, benchmarking its performance in a realistic framework and comparing results with a commercial graphic processing unit (GPU). Our results indicate a 4 orders-of-magnitude increase in energy efficiency and a 3 orders-of-magnitude increase in area efficiency for the same throughput of a digital solution, supporting IMC for energy efficient pre- and post-processing in next-generation B5G and 6G networks.

An Analogue In-Memory Ridge Regression Circuit With Application to Massive MIMO Acceleration