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A 12-bit time-interleaved (TI) analog-to-digital converter (ADC) with pipelined successive-approximation (SAR) channels is presented in this paper. The ADC consists of four TI channels, each incorporating a two-stage pipelined asynchronous SAR ADC. To facilitate clock distribution, a common bootstrapped sampler in front of the four channels is employed. The reset switch in the capacitive digital-to-analog converter (CDAC) of each channel is also bootstrapped to enhance the speed and linearity. A prototype ADC has been designed and implemented in a 22-nm FDSOI CMOS technology, with a core occupation area of 0.43 mm 2 . Measurements show that the ADC achieves a signal-to-noise-and-distortion ratio of 50dB with a low-frequency input, and of 48.5 dB at Nyquist. The total power consumption is 37.5 mW; the core ADC consumes 19.3 mW from a 0.8V supply. With a 1.4 GS/s sampling rate and input at Nyquist, the ADC achieves a Walden&#x2019;s figure of merit of 114 fJ/conversion.

A 12-bit High-Speed Time-Interleaved Pipelined Asynchronous Successive-Approximation ADC in 22-nm FDSOI CMOS