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In multi-core heterogeneous systems, communication on the data bus/NoC (Network-on-Chip) is complex. To ensure low-latency transmission of high-level messages, such as control messages, configuration instructions, and status information, while maintaining the efficiency of data bus/NoC transmission, we propose the concept of a message bus. In this paper, we present a lightweight and high-throughput asynchronous message bus capable of receiving and forwarding messages from different synchronous domains. A Quasi-Synchronous communication mechanism is proposed, where flits from the transmitter can be transmitted at fixed intervals without waiting for the ready signal from the receiver. This resolve the additional latency introduced by asynchronous handshaking, particularly in long-wire transmissions. Instead of flit-level handshaking, we introduce a packet-level flow control mechanism to avoid data overflow. Furthermore, we propose a novel Asynchronous Blocking Retransmission Buffer (ABRB) to address the communication congestion where subsequent packets are blocked by preceding ones. The packets can be sequentially written into the ABRB, enabling partial parallel transmission. For various benchmarks, the proposed asynchronous message bus achieves significant performance and energy consumption improvements compared to the synchronous baseline, at the cost of some additional area overhead and more design effort.

A Lightweight and High-Throughput Asynchronous Message Bus for Communication in Multi-Core Heterogeneous Systems