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This study explores the application of Generative Adversarial Networks (GANs) for generating wafer-level Wafer Acceptance Test (WAT) and Chip Probe (CP) test data in chip manufacturing processes, with a focus on Design-Technology Co-Optimization (DTCO). The generated virtual silicon data encompasses essential performance characteristics, physical electrical properties, wafer-level process parameter distributions, as well as implicit information about wafer-level uniformity and defects. This information represents non-random features on wafers, such as similar distorted wafer surfaces observed in lots produced from various batches. This innovative approach overcomes data acquisition barriers, efficiently compresses large datasets while ensuring data confidentiality, and holds immense potential for the development of advanced Electronic Design Automation (EDA) tools, enabling the synergistic optimization of manufacturing processes and chip design flow.

Application of Generative Adversarial Networks for Virtual Silicon Data Generation and Design-Technology Co-Optimization: A Study on WAT and CP