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To predict long term device aging under use bias, models extracted from voltage accelerated tests must be extrapolated into the future. The traditional model uses a power law, to linearly fit the test data on a log-log plot, and then extrapolates aging kinetics. The challenge is that the measured data do not always follow a straight line on the log-log plot, calling the accuracy of such prediction into question. Although there are models that can fit test data well in this case, their prediction capability for future aging is typically not verified. The key advance of this work is the development of a methodology for extracting models that can verifiably predict future aging over a wide (Vg, Vd) bias space, when aging kinetics do not follow a simple power law. This is achieved by experimentally separating aging into four types of traps and modelling each of them by a straight line individually. The applicability of this methodology is verified on 3 different CMOS processes where it can predict aging at least 3 orders of magnitude into the future. The contributions of each type of traps across the (Vg, Vd) space are mapped. It is also shown that good fitting with test data does not warrant good prediction, so that good fitting should not be used as the only criterion for validating a model.

A Pragmatic Model to Predict Future Device Aging