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This paper presents the design of a buck converter for use in low-power system-on-chips (SoCs) with a ripple voltage small enough to directly power sensitive analog circuits without the help of low-dropout voltage regulators (LDOs). To minimize the ripple voltage while maximizing the converter&#x2019;s light load efficiency, we employ a pulse-frequency modulation (PFM) scheme and a fast duty-cycled comparator to control the converter&#x2019;s output voltage. The duty cycling of the comparator, automatically performed by the Sleep State Controller (SSC), helps improve the light-load efficiency by 48%. Fabricated in a 0.18-&#x03BC;m CMOS process with an active area of 0.42 mm 2 , the proposed low-ripple buck converter achieves the ripple voltage of 1.6 mV pp  and the overall efficiency of higher than 74.4% over the load current range from 1.2 &#x03BC;A to 1.8 mA.

Design of A High-Efficiency Low-Ripple Buck Converter for Low-Power System-On-Chips