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Conventional high-performance flip-flops suffer from large power consumption at the nominal supply region and unreliable operation in the low-voltage region. To overcome these drawbacks, this paper proposes conditional-bridging flip-flops (CBFFs) that can conditionally activate the shorting device in the sense-amplifier stage. There are two versions of the proposed flip-flop. The single-ended version (CBFF-S) adopts a single-ended latching stage to optimize in terms of power consumption and area. For applications requiring high speed with differential outputs, the speed-optimized differential version (CBFF-D) is also proposed. Since the shorting device is adaptively turned on only when it is necessary, the flip-flops have fully static operations with reduced switching power consumption. The conditional bridging technique can also help minimize the effective parasitic capacitance relevant to the shorting device by relieving the design burden of weakening the device, resulting in further power reduction. The technique also provides the complete separation of complementary precharge nodes in the sense-amplifier stage during input sampling, achieving a fast and reliable operation. To further reduce power consumption and latency, the latching stage is designed to have no glitches and signal fighting, and to be driven by the output of the sense-amplifier stage without signal inversion. Moreover, the conditionally bridged sense-amplifier stage having a reliable pull-down of precharge nodes and the latching stage having a contention-free operation allow the flip-flops to provide stable operation down to the near-threshold voltage (NTV) region. The proposed flip-flops were designed in a 28-nm CMOS process, whose performance evaluation results indicated that the power consumption of CBFF-S is reduced by up to 56.2% compared to conventional single-ended flip-flops at 0.1 switching activity. The minimum DQ latency was also reduced by up to 33.6%. They also indicated that CBFF-D offers up to 33.8% less power at 0.1 switching activity, and up to 24.1% lower minimum DQ latency than those of conventional differential flip-flops. The resulting power-delay product (PDP) of CBFFs was at least 27.8% less than those of conventional flip-flops. The Monte-Carlo simulation results considering the process, voltage, and temperature (PVT) variations indicated that CBFFs could operate reliably down to a supply voltage of 0.3 V.

Low-Power High-Speed Sense-Amplifier-Based Flip-Flops with Conditional Bridging