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In this article, we propose a novel vertical TFET that benefits from dual doping-less tunneling junction. Due to the low on-state current of silicon-based TFETs, we employ a dual-source configuration and a high-k dielectric material in the oxide region. The performance assessment of our device is thoroughly investigated using the Silvaco ATLAS device simulator. By activating models such as trap-assisted tunneling and interface trap charge for all the simulations our obtained results are less-ideal but closer to the experimental expectations. We also investigate the impact of Yttrium-doped hafnium, a well-known negative capacitance material, on our device performance. Parameters such as  I on   of 59.9&#x03BC;A/&#x03BC;m and  I on /I off   ratio of 2.95&#x00D7;10 8  show that our Si-based device is a notable candidate for CMOS applications.

A Novel Vertical Si TFET with Dual Doping-Less Tunneling Junction: A Simulation Study Including Trap-Related Non-Idealities