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This paper proposes a self-aligned sub-harmonically injection locked phase locked loop (SILPLL) in 180-nm Semi Conductor Laboratory (SCL) CMOS technology. In this work, an aperture phase detector (APD) based delay locked loop (DLL) with windowing technique is proposed to dynamically align the injection timing of pulse with the rising edge of sub-harmonically injection locked voltage controlled oscillator. In contrast to classical self-aligned SILPLL, this work replaces the commonly deployed tri-state based phase frequency detector (PFD) in DLL by an APD, which becomes active over a pulse-window. The APD deployed in DLL reduces the in-band phase noise due to the charge pump by 12 dBc at 200 KHz offset in comparison with the classical self-aligned DLL. A detailed mathematical model of the self-aligned injection with noise sources is presented for the proposed architecture. Additionally, this work includes noise analysis with the effect of different design aspects such as locking range, and realignment factor. The proposed architecture operates at 1.8 GHz output frequency, and the simulated phase noise is -120.6 dBc/Hz at 1 MHz offset with an integrated root-mean-square jitter of 0.96 ps from 10 kHz to 30 MHz. The implemented PLL consumes 6.6 mW from 1.8 V power supply.

A Low-Phase-Noise Self-Aligned Sub-Harmonically Injection-Locked PLL using Aperture Phase Detector-based DLL Windowing Technique