English (United Kingdom)

https://curated-unify.zendy.io/wp-json/zendy-region/v1/featured_content/oa?rat=en

https://curated-unify.zendy.io/wp-json/zendy-region/v1/highlighted_journal/

Global: Zendy Plus annual

Presents the access of premium content as premium feature

Premium Content

Presents the keyphrase highlighting as premium feature

Keyphrase Highlighting

Presents the summarisation as premium feature

Summarisation

Insights

Presents the pdf analysis as premium feature

PDF Analysis

Presents the zaia usage as premium feature

ZAIA

Global: Zendy Tools annual

Global: Zendy Free Plan

Global: Zendy Tools monthly

Global: Zendy Plus monthly

This paper presents the hardware design of fast and low-cost denoising filters suitable to be exploited in the enabling technologies for Industry 5.0. A novel approximate computing strategy is introduced to reduce the computational complexity of the image denoising operation and to comply with real-time requirements. Firstly, it is demonstrated that the novel approximate approach can be helpfully exploited in the design of reconfigurable denoising filters able to reach image qualities as close as possible to the precise software counterparts. The reconfigurability leads to hardware architectures run-time adaptable to different levels of noise, whereas the adopted approximation strategy limits hardware resources and energy requirements. Quality tests, performed at various image and kernel sizes, and noise standard deviations, demonstrate that the approximate denoising approach presented here reaches PSNR and SSIM comparable with the precise denoise filtering. In comparison with state-of-the-art FPGA-based competitors, the novel filters reduce the resources requirements by up to 70%, achieve frame rates up to 35 times higher, and dissipate more than 45% lower power. When implemented within the XC7Z7020 FPGA device, a 5&#x00D7;5 filter designed as proposed here denoises 512&#x00D7;512 grayscale images using only 1689 LUTs, 2635 Flip-Flops and 32 DSPs. Moreover, it processes up to 926.8 frames per second, consumes just 63mW @ 244MHz and, with a noise standard deviation equal to 10, it achieves an average PSNR of ~ 33dB with an average SSIM of ~ 0.86.

Design of Approximate Bilateral Filters for Image Denoising on FPGAs