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Soft errors, aging effects and process variations have become the three most critical reliability issues for nanoscale complementary metal oxide semiconductor (CMOS) circuits. In this paper, the effects of bias temperature instability (BTI) and process variations on the threshold voltage of MOS devices are theoretically deduced, and the drift of the threshold voltage under the synergistic effect of BTI and process variations is analyzed. Based on the deduced threshold voltage drift formula under the synergistic effect, the critical charge and delay of different logic gates under different aging times in NanGate&#x2019;s 45 nm process are simulated and analyzed. A method based on the change in the critical charge and delay of the soft error rate (SER) calculation considering BTI effect and process variations is given, and the effectiveness of our method comprehensively demonstrated using the ISCAS85,89 benchmarks. As a result, we can observe that the effect of only considering the BTI effect on the critical charge of the circuit is smaller than that of considering both the BTI effect and process variations. The simulation results show that with increasing aging time, the synergistic effect of BTI and process variations makes the increase in the soft error rate more serious than the impact of either effect alone.

Synergistic Effect of BTI and Process Variations on the Soft Error Rate Estimation in Digital Circuits