Modelling of FEOL and BEOL Amorphous Gallium Oxide-based Ferroelectric FETs with a Metal Interlayer for Multilevel Operation in Short Channel Devices

Ferroelectric field effect transistors (FeFETs) are among the most promising candidates for the implementation of artificial synapses for neuromorphic computing. However, their scaling poses big challenges, as multilevel behavior is hindered by the two-level or very-few-level polarization behavior reported for devices featuring an aggressive lateral scaling. Moreover, the switching and stabilization of ferroelectric polarization, and consequently the device operation, is inherently linked to high levels of charge trapping in the gate stack, limiting the reliability and increasing the variability of the FeFETs. In this work we investigate, by means of calibrated TCAD simulations, FeFETs integrating a metal interlayer inside the gate stack. FeFETs are designed so that, by properly biasing the device, the metal interlayer can get charged thanks to charge tunneling through the dielectric layer. We first investigate a conventional front-end-of-line implementation, consisting of an aggressively scaled FeFET featuring a ferroelectric hafnium zirconium oxide and a dielectric hafnium oxide in the gate stack, a single-crystal silicon channel, and highly-doped source and drain pockets. Then we consider a back-end-of-line compatible device structure featuring lightly– doped amorphous gallium-oxide channel material, with Schottky-type tungsten contacts. We show that, for both architectures, the charge in the metal interlayer can effectively stabilize the ferroelectric polarization, even for a negligible charge trapping in the dielectric stack. Moreover, the interplay between ferroelectric polarization and charge in the metal interlayer enables a multilevel operation even for a uniform ferroelectric polarization.