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Processor performance is measured by amount of ILP (Instruction Level Parallelism) represented by its design. this parallelism is limited by the execution of conditional branch instructions which may break the flow of the program execution. To overcome this problem, several ways were suggested in order to predict both the direction of instructions execution and the address of the instruction to be executed next. In this paper, a design for a dynamic branch predictor was implemented in VHDL (VHSIC Hardware Description Language) then it was integrated with FPGA (Field Programmable Gate Arrays) MIPS (Microprocessor without Interlocked Pipelined Stages) processor and its ability to increase prediction accuracy and MIPS processor performance was approved. This predictor combines gshare and bimodal branch prediction techniques by dividing the PHT (Pattern History Table) into two branch streams corresponding to taken and not-taken states. This combined branch predictor was synthesized using the XILINX ISE (Integrated Software Environment) Design Suite 14.7 tool.

Selective branch prediction schemes based on FPGA MIPS processor for educational purposes