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A 33.6 ps LSB Time-to-Digital converter was designed in 130 nm BiCMOStechnology. The core of the converter is a differential 9-stage ringoscillator, based on a multi-path architecture. A novel version of this designis proposed, along with an analytical model of linearity. The model allowed usto understand the source of the performance superiority (in terms of linearity)of our design and to predict further improvements. The oscillator is integratedin a event-by-event self-calibration system that allows avoiding any PLL-basedsynchronization. For this reason and for the compactness and simplicity of thearchitecture, the proposed TDC is suitable for applications in which a largenumber of converters and a massive parallelization are required such asHigh-Energy Physics and medical imaging detector systems. A test chip for theTDC has been fabricated and tested. The TDC shows a DNL$\leq$1.3 LSB, anINL$\leq$2 LSB and a single-shot precision of 19.5 ps (0.58 LSB). The chipdissipates a power of 5.4 mW overall.

A massively scalable Time-to-Digital Converter with a PLL-free calibration system in a commercial 130 nm process