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The gate‐all‐around nanowire transistor, due to its extremely tight electrostatic control and vertical integration capability, is a highly promising candidate for sub‐5 nm technology nodes. In particular, the junctionless nanowire transistors are highly scalable with reduced variability due to avoidance of steep source/drain junction formation by ion implantation. Here a dual‐gated junctionless nanowire p‐type field effect transistor is demonstrated using tellurium nanowire as the channel. The dangling‐bond‐free surface due to the unique helical crystal structure of the nanowire, coupled with an integration of dangling‐bond‐free, high quality hBN gate dielectric, allows for a phonon‐limited field effect hole mobility of 570 cm 2  V −1  s −1  at 270 K, which is well above state‐of‐the‐art strained Si hole mobility. By lowering the temperature, the mobility increases to 1390 cm 2  V −1  s −1  and becomes primarily limited by Coulomb scattering. The combination of an electron affinity of  ≈ 4 eV and a small bandgap of tellurium provides zero Schottky barrier height for hole injection at the metal‐contact interface, which is remarkable for reduction of contact resistance in a highly scaled transistor. Exploiting these properties, coupled with the dual‐gated operation, we achieve a high drive current of 216 μA μm −1  while maintaining an on‐off ratio in excess of 2  ×  10 4 . The findings have intriguing prospects for alternate channel material based next‐generation electronics.

Contact‐Barrier Free, High Mobility, Dual‐Gated Junctionless Transistor Using Tellurium Nanowire