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Memory bandwidth is known to be a performance bottleneck for FPGAaccelerators, especially when they deal with large multi-dimensional data-sets.A large body of work focuses on reducing of off-chip transfers, but few authorstry to improve the efficiency of transfers. This paper addresses the laterissue by proposing (i) a compiler-based approach to accelerator's data layoutto maximize contiguous access to off-chip memory, and (ii) data packing andruntime compression techniques that take advantage of this layout to furtherimprove memory performance. We show that our approach can decrease the I/Ocycles up to $7\times$ compared to un-optimized memory accesses.

An Irredundant and Compressed Data Layout to Optimize Bandwidth Utilization of FPGA Accelerators