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Analog-Based In-Memory Computing (AIMC) inference accelerators can be used toefficiently execute Deep Neural Network (DNN) inference workloads. However, tomitigate accuracy losses, due to circuit and device non-idealities,Hardware-Aware (HWA) training methodologies must be employed. These typicallyrequire significant information about the underlying hardware. In this paper,we propose two Post-Training (PT) optimization methods to improve accuracyafter training is performed. For each crossbar, the first optimizes theconductance range of each column, and the second optimizes the input, i.e,Digital-to-Analog Converter (DAC), range. It is demonstrated that, when thesemethods are employed, the complexity during training, and the amount ofinformation about the underlying hardware can be reduced, with no notablechange in accuracy ($\leq$0.1%) when finetuning the pretrained RoBERTatransformer model for all General Language Understanding Evaluation (GLUE)benchmark tasks. Additionally, it is demonstrated that further optimizinglearned parameters PT improves accuracy.

Improving the Accuracy of Analog-Based In-Memory Computing Accelerators Post-Training