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Quantum low-density parity-check (qLDPC) codes are a promising constructionfor drastically reducing the overhead of fault-tolerant quantum computing(FTQC) architectures. However, all of the known hardware implementations ofthese codes require advanced technologies, such as long-range qubitconnectivity, high-weight stabilizers, or multi-layered chip layouts. Analternative approach to reduce the hardware overhead of fault-tolerance is touse bosonic cat qubits where bit-flip errors are exponentially suppressed bydesign. In this work, we combine both approaches and propose an architecturebased on cat qubits concatenated in classical LDPC codes correcting forphase-flips. We find that employing such phase-flip LDPC codes provides twomajor advantages. First, the hardware implementation of the code can berealised using short-range qubit interactions in 2D and low-weight stabilizers,which makes it readily compatible with current superconducting circuittechnologies. Second, we demonstrate how to implement a fault-tolerantuniversal set of logical gates with a second layer of cat qubits whilemaintaining the local connectivity. We conduct a numerical brute forceoptimisation of these classical codes to find the ones with the best encodingrate for algorithmically relevant code distances. We discover that some of thebest codes benefit from a cellular automaton structure. This allows us todefine families of codes with high encoding rates and distances. Finally, wenumerically assess the performance of our codes under circuit-level noise.Assuming a physical phase-flip error probability $\epsilon \approx 0.1\%$, our$[165+8\ell, 34+2\ell, 22]$ code family allows to encode $100$ logical qubitswith a total logical error probability (including both logical phase-flip andbit-flip) per cycle and per logical qubit $\epsilon_L \leq 10^{-8}$ on a $758$cat qubit chip.

LDPC-cat codes for low-overhead quantum computing in 2D