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Microarchitectural attacks compromise security by exploiting software-visibleartifacts of microarchitectural optimizations such as caches and speculativeexecution. Defending against such attacks at the software level requires anappropriate abstraction at the instruction set architecture (ISA) level thatcaptures microarchitectural leakage. Hardware-software leakage contracts haverecently been proposed as such an abstraction. In this paper, we propose asemi-automatic methodology for synthesizing hardware-software leakage contractsfor open-source microarchitectures. For a given ISA, our approach relies onhuman experts to (a) capture the space of possible contracts in the form ofcontract templates and (b) devise a test-case generation strategy to explore amicroarchitecture's potential leakage. For a given implementation of an ISA,these two ingredients are then used to automatically synthesize the mostprecise leakage contract that is satisfied by the microarchitecture. We haveinstantiated this methodology for the RISC-V ISA and applied it to the Ibex andCVA6 open-source processors. Our experiments demonstrate the practicalapplicability of the methodology and uncover subtle and unexpected leaks.

Synthesizing Hardware-Software Leakage Contracts for RISC-V Open-Source Processors