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Dense Matrix Multiplication (MatMul) is arguably one of the most ubiquitouscompute-intensive kernels, spanning linear algebra, DSP, graphics, and machinelearning applications. Thus, MatMul optimization is crucial not only inhigh-performance processors but also in embedded low-power platforms. SeveralInstruction Set Architectures (ISAs) have recently included matrix extensionsto improve MatMul performance and efficiency at the cost of added matrixregister files and units. In this paper, we propose Matrix eXtension (MX), alightweight approach that builds upon the open-source RISC-V Vector (RVV) ISAto boost MatMul energy efficiency. Instead of adding expensive dedicatedhardware, MX uses the pre-existing vector register file and functional units tocreate a hybrid vector/matrix engine at a negligible area cost (< 3%), whichcomes from a compact near-FPU tile buffer for higher data reuse, and no clockfrequency overhead. We implement MX on a compact and highly energy-optimizedRVV processor and evaluate it in both a Dual- and 64-Core cluster in a 12-nmtechnology node. MX boosts the Dual-Core's energy efficiency by 10% for adouble-precision 64x64x64 matrix multiplication with the same FPU utilization(~97%) and by 25% on the 64-Core cluster for the same benchmark on 32-bit data,with a 56% performance gain.

MX: Enhancing RISC-V's Vector ISA for Ultra-Low Overhead, Energy-Efficient Matrix Multiplication