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Chiplet-based systems have gained significant attention in recent years dueto their low cost and competitive performance. As the complexity andcompactness of a chiplet-based system increase, careful consideration must begiven to microbump assignments, interconnect delays, and thermal limitationsduring the floorplanning stage. This paper introduces RLPlanner, an efficientearly-stage floorplanning tool for chiplet-based systems with a novel fastthermal evaluation method. RLPlanner employs advanced reinforcement learning tojointly minimize total wirelength and temperature. To alleviate thetime-consuming thermal calculations, RLPlanner incorporates the developed fastthermal evaluation method to expedite the iterations and optimizations.Comprehensive experiments demonstrate that our proposed fast thermal evaluationmethod achieves a mean absolute error (MAE) of 0.25 K and delivers over 120xspeed-up compared to the open-source thermal solver HotSpot. When integratedwith our fast thermal evaluation method, RLPlanner achieves an averageimprovement of 20.28\% in minimizing the target objective (a combination ofwirelength and temperature), within a similar running time, compared to theclassic simulated annealing method with HotSpot.

RLPlanner: Reinforcement Learning based Floorplanning for Chiplets with Fast Thermal Analysis