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Extended reality (XR) applications are Machine Learning (ML)-intensive,featuring deep neural networks (DNNs) with millions of weights, tightlylatency-bound (10-20 ms end-to-end), and power-constrained (low tens of mW).While ML performance and efficiency can be achieved by introducing neuralengines within low-power systems-on-chip (SoCs), system-level power fornontrivial DNNs depends strongly on the energy of non-volatile memory (NVM)access for network weights. This work introduces Siracusa, a near-sensorheterogeneous SoC for next-generation XR devices manufactured in 16 nm CMOS.Siracusa couples an octa-core cluster of RISC-V digital signal processing coreswith a novel tightly-coupled "At-Memory" integration between a state-of-the-artdigital neural engine called N-EUREKA and an on-chip NVM based onmagnetoresistive memory(MRAM), achieving 1.7x higher throughput and 4.1x betterenergy efficiency than XR SoCs using MRAM as background memory. The fabricatedSoC prototype achieves an area efficiency of 65.2 GOp/s/mm2 and a peak energyefficiency of 8.84 TOp/J for DNN inference while supporting complexheterogeneous application workloads, which combine ML with conventional signalprocessing and control.

Siracusa: A 16 nm Heterogenous RISC-V SoC for Extended Reality with At-MRAM Neural Engine